1. Field of the Invention
The present invention relates to a substrate, and more specifically, to a substrate having a plurality of electrodes formed on a base material to protrude and a semiconductor device using the substrate.
Priority is claimed on Japanese Patent Application No. 2012-081929, filed Mar. 30, 2012, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
A semiconductor device having a three-dimensional structure has attracted interest as an effective structure which avoids various obstacles with which a semiconductor device having a two-dimensional structure has been confronted, such as limits of lithography techniques in miniaturization, increase of wiring resistance caused by miniaturization of a wiring or by increase of wiring length, increase of parasitic effects, tendency of the operation speed to be saturated along therewith, and high electrical field effects due to miniaturization in element dimension, and continues to be improved in integration level by integrating semiconductor elements three-dimensionally in a stacked multi-layer structure by stacking semiconductor active layers.
In manufacturing a semiconductor device having a three-dimensional structure, a stacked-type semiconductor device constructed by bonding wafers having many minute electrodes formed thereon is considered.
For such a stacked-type semiconductor device, in order to protect bonded electrodes, a resin may be injected into a gap between wafers. Here, when many minute electrodes are formed, the gap between wafers becomes smaller and it becomes difficult to inject a resin into the gap. Regarding this problem, techniques for maintaining a gap between wafers by providing an insulating spacer on a stacking surface of a wafer are disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-114350.